Nehalem

Here comes Intel's Nehalem, the next big thing for the desktop, server, and mobile processors. Intel used the Spring IDF 2008 as a showcase for its new Nehalem processor architecture. Nehalem will also incorporate Simultaneous Multithreading (SMT) which is also known as Hyper-Threading (HT). The really big thing is the integrated memory controller, which AMD has used to great advantage for quite some time now.

Intel's Nehalem is truly a radical architecture departure from Intel thanks to its integrated memory controller that will support triple-channel DDR3-1333 memory. This won't be the only design element taken almost verbatim from AMD's playbook; Intel also plans to incorporate the new QuickPath Interface on Nehalem. QuickPath is almost identical in spirit and implementation to AMD's current interconnect technology, HyperTransport.

The first available Nehalem processors will be built on the existing 45nm manufacturing process, will incorporate SSE4 instructions, and will feature four fully integrated cores. Each core will have its own dedicated 256KB L2 cache and each core will share an 8MB of L3 cache pool. The bulk of these 731 million transistor processors are dedicated to cache.

Nehalem launch date in Q4 2008, with a simulteanous rollout for servers and desktops. Since Nehalem uses a new architecture and transport bus, existing motherboards will not work with the new processors.

Big caches for more performance seems to be the use chip manufacturers put all the extra transistors to, instead of the likely deadend of new architecture. Anyone seen the Itanitc lately, or even care? Caches is not the be all to end all of performance, but if you have the transistors, it helps.

More here.